Initial load capacitance inherent in signal load lines such as input and output (I/O) lines extending between a memory and another semiconductor device such as a processor, for example, can cause degradation in the early portion of pulse wave or other driving signals applied to those load lines following a high impedance state of the lines. This problem often manifests as a short or “thin” first pulse relative to the ensuing pulses following in the applied pulse wave signal applied after the high impedance condition of the load line.
One existing solution uses a series of “pre-charge” pulses applied to the signal load line prior to application of the pulse signal proper. The pre-charge pulse is not a driving signal per se, it contains no useful information, and is only used to temporarily compensate for the inherent initial load capacitance common in many signal load lines. Accordingly, this technique wastes time and energy.
Another existing solution is to configure the drive circuit with a low internal impedance to approximately match the zero start impedance of the signal load line to thereby apply a large drive current which is used for all signal pulses regardless of whether it is the initial pulse or any pulse subsequent to the first pulse. However, this too wastes energy. Further, the larger drive current developed for all pulses of the pulse wave signal can introduce other errors including, for example, simultaneous switching of output (SSO) errors.
Although a reduction in the length of the signal lines would be helpful to minimize the negative effects of the inherent capacitive characteristics thereof, in many cases it is not possible or practical to relocate the circuit components into closer mutual proximity.